As advances in processing technology allow for an increasing number of devices to be fabricated on a single integrated circuit (IC), the surface area or size of each individual device on the IC is scaled down or reduced. Conductive lines or interconnect structures that electrically couple such individual devices are also scaled. However, the same scaling factor applied to line width and line-to-line spacing is not generally applied to interconnect line thickness due to the need to maintain minimum current-carrying capacity. Thus, interconnect lines are often thicker than those for which the scaling factor employed for the line width would predict.
Adjacent interconnect lines form parasitic capacitors. The plate area of each plate of the capacitor formed is the product of the length of the line and its thickness over that length. The capacitances of such capacitors are directly proportional to the area of the capacitor plates and the dielectric constant of the dielectric material disposed between the plates and inversely proportional to the distance between the capacitor plates (line-to-line spacing). Thus, as IC's are scaled down in size, the line-to-line spacing decreases. In addition, the number of lines that are needed to interconnect the increased number of devices also increases, resulting in an increase in the line-to-line capacitance. In some high-speed circuits, this interconnect capacitance can be the limiting factor in the speed of the integrated circuit. Thus it is desirable to reduce the interconnect capacitance.
A significant factor in the value of the interconnect capacitance is the dielectric constant of the materials that surround the interconnect lines, as capacitance is directly proportional to the dielectric constant. Therefore, to reduce the capacitance of the interconnect structure, low dielectric constant (k) materials have been increasingly used. However, it has been found that use of such low dielectric constant (low-k) materials is often problematic.
FIG. 1 illustrates a typical interconnect structure. Metal lines 2 are formed in a low-k dielectric layer 4. A cap layer 6 is formed on the low-k dielectric layer 4 and metal lines 2. It has been found that the interface 10 between metal lines 2 and cap layer 6 is electrically weak. Due to the different voltages in the metal lines, leakage current may exist between the metal lines, which causes electrical migration. Copper inside the metal lines 2 therefore diffuses along the interface 10. As a result, the reliability of the integrated circuit is adversely affected, and the mean time to failure (MTTF) is reduced.
What is needed in the art, therefore, is an interconnect structure that may incorporate low-k dielectric materials to take advantage of the benefits associated with reduced capacitance while at the same time overcoming the deficiencies of the prior art.